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<center><span style="font-size: 24px; font-family: "times new roman", times, serif; color: rgb(39,87,141)"><b>Xilinx XC2V500 Virtex-II XC2V500-4FG456I IC FPGA 264 I/O 456 FBGA (8333)I<br></b></span><font color="#27578d" face="times new roman, times, serif"><b>New, OLD STOCK (2001). In excellent cosmetic condition. Close up photo of chip is provided, please see pictures for detail. Sealed bag was opened briefly for photos then resealed afterwards. These came from a large well known local thermal camera manufacturer.</b></font></center></td></tr></tbody></table>
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<p style="margin-right: 0px" dir="ltr"><span style="color: rgb(0,0,0)"><span style="font-size: 20px"><span style="font-family: "times new roman", times, serif"><strong><u>Manufacturer</u></strong>: Xilinx<br><strong><u>Model</u></strong>: XC2V500-4FG456I<br><br><strong><u>Includes</u></strong>:</span></span></span></p><p style="margin-right: 0px" dir="ltr"></p><ul><li><span style="font-family: "times new roman", times, serif; font-size: 20px; color: rgb(0, 0, 0);">Virtex-II ($125 per chip)</span></li></ul><span style="color: rgb(0,0,0)"><span style="font-size: 20px"><span style="font-family: "times new roman", times, serif"><br><strong><u>Specifications</u></strong>: (<strong>These specifications were taken from the manufacturers website</strong>)</span></span></span><p></p><p style="margin-right: 0px" dir="ltr"></p><ul><li><span style="font-family: "times new roman", times, serif; font-size: 20px; color: rgb(0, 0, 0);">Series: Virtex®-II</span></li><li><span style="font-family: "times new roman", times, serif; font-size: 20px; color: rgb(0, 0, 0);">Number of LABs/CLBs: 768</span></li><li><span style="font-family: "times new roman", times, serif; font-size: 20px; color: rgb(0, 0, 0);">Total RAM Bits: 589824</span></li><li><span style="font-family: "times new roman", times, serif; font-size: 20px; color: rgb(0, 0, 0);">Number of I/O: 264</span></li><li><span style="font-family: "times new roman", times, serif; font-size: 20px; color: rgb(0, 0, 0);">Number of Gates: 500000</span></li><li><span style="font-family: "times new roman", times, serif; font-size: 20px; color: rgb(0, 0, 0);">Voltage - Supply: 1.425V ~ 1.575V</span></li><li><span style="font-family: "times new roman", times, serif; font-size: 20px; color: rgb(0, 0, 0);">Mounting Type: Surface Mount</span></li><li><span style="font-family: "times new roman", times, serif; font-size: 20px; color: rgb(0, 0, 0);">Operating Temperature: -40°C ~ 100°C (TJ)</span></li><li><span style="font-family: "times new roman", times, serif; font-size: 20px; color: rgb(0, 0, 0);">Package / Case: 456-BBGA</span></li><li><span style="font-family: "times new roman", times, serif; font-size: 20px; color: rgb(0, 0, 0);">Supplier Device Package: 456-FBGA (23x23)</span></li><li><span style="font-family: "times new roman", times, serif; font-size: 20px; color: rgb(0, 0, 0);">Base Product Number: XC2V500</span></li><li><span style="font-family: "times new roman", times, serif; font-size: 20px; color: rgb(0, 0, 0);">Manufacture Year: 2001</span></li></ul><span style="color: rgb(0,0,0)"><span style="font-size: 20px"><span style="font-family: "times new roman", times, serif"><br><strong><u>Summary of Virtex-II Features</u></strong>: (<strong>These features are directly from the Xilinx Data Sheet, available online from the manufacturers website)</strong></span></span></span><p></p><p style="margin-right: 0px" dir="ltr"></p><ul><li><span style="color: rgb(0, 0, 0); font-family: "times new roman", times, serif; font-size: 20px;">Industry First Platform FPGA Solution</span></li></ul><div><font color="#000000" face="times new roman, times, serif"><span style="font-size: 20px;"><br></span></font></div><ul><li><span style="color: rgb(0, 0, 0); font-family: "times new roman", times, serif; font-size: 20px;">IP-Immersion Architecture</span></li></ul><p></p><blockquote style="margin: 0 0 0 40px; border: none; padding: 0px;"><p style="margin-right: 0px" dir="ltr"><span style="color: rgb(0, 0, 0); font-family: "times new roman", times, serif; font-size: 20px;">- Densities from 40K to 8M system gates</span></p><p style="margin-right: 0px" dir="ltr"><span style="color: rgb(0, 0, 0); font-family: "times new roman", times, serif; font-size: 20px;">- 420 MHz internal clock speed (Advance Data)</span></p><p style="margin-right: 0px" dir="ltr"><span style="color: rgb(0, 0, 0); font-family: "times new roman", times, serif; font-size: 20px;">- 840+ Mb/s I/O (Advance Data)</span></p><p style="margin-right: 0px" dir="ltr"><span style="color: rgb(0, 0, 0); font-family: "times new roman", times, serif; font-size: 20px;"><br></span></p></blockquote><p style="margin-right: 0px" dir="ltr"></p><ul><li><span style="color: rgb(0, 0, 0); font-family: "times new roman", times, serif; font-size: 20px;">SelectRAM™ Memory Hierarchy</span></li></ul><p></p><blockquote style="margin: 0 0 0 40px; border: none; padding: 0px;"><p style="margin-right: 0px" dir="ltr"><span style="color: rgb(0, 0, 0); font-family: "times new roman", times, serif; font-size: 20px;">- 3 Mb of dual-port RAM in 18 Kbit block SelectRAM resources</span></p><p style="margin-right: 0px" dir="ltr"><span style="color: rgb(0, 0, 0); font-family: "times new roman", times, serif; font-size: 20px;">- Up to 1.5 Mb of distributed SelectRAM resources</span></p><p style="margin-right: 0px" dir="ltr"><span style="color: rgb(0, 0, 0); font-family: "times new roman", times, serif; font-size: 20px;"><br></span></p></blockquote><font face="Times New Roman" size="4"><ul><li><font face="Times New Roman" size="4" color="#000000">High-Performance Interfaces to External Memory</font></li></ul></font><blockquote style="margin: 0 0 0 40px; border: none; padding: 0px;"><p style="margin-right: 0px" dir="ltr"><span style="color: rgb(0, 0, 0); font-family: "times new roman", times, serif; font-size: 20px;">- DRAM interfaces</span></p><p style="margin-right: 0px" dir="ltr"><span style="color: rgb(0, 0, 0); font-family: "times new roman", times, serif; font-size: 20px;">· SDR / DDR SDRAM</span></p><p style="margin-right: 0px" dir="ltr"><span style="color: rgb(0, 0, 0); font-family: "times new roman", times, serif; font-size: 20px;">· Network FCRAM</span></p><p style="margin-right: 0px" dir="ltr"><span style="color: rgb(0, 0, 0); font-family: "times new roman", times, serif; font-size: 20px;">· Reduced Latency DRAM</span></p><p style="margin-right: 0px" dir="ltr"><span style="color: rgb(0, 0, 0); font-family: "times new roman", times, serif; font-size: 20px;">- SRAM interfaces</span></p><p style="margin-right: 0px" dir="ltr"><span style="color: rgb(0, 0, 0); font-family: "times new roman", times, serif; font-size: 20px;">· SDR / DDR SRAM</span></p><p style="margin-right: 0px" dir="ltr"><span style="color: rgb(0, 0, 0); font-family: "times new roman", times, serif; font-size: 20px;">· QDR™ SRAM</span></p><p style="margin-right: 0px" dir="ltr"><span style="color: rgb(0, 0, 0); font-family: "times new roman", times, serif; font-size: 20px;">- CAM interfaces</span></p><p style="margin-right: 0px" dir="ltr"><span style="color: rgb(0, 0, 0); font-family: "times new roman", times, serif; font-size: 20px;"><br></span></p></blockquote><p style="margin-right: 0px" dir="ltr"></p><ul><li><span style="color: rgb(0, 0, 0); font-family: "times new roman", times, serif; font-size: 20px;">Arithmetic Functions</span></li></ul><p></p><blockquote style="margin: 0 0 0 40px; border: none; padding: 0px;"><p style="margin-right: 0px" dir="ltr"><span style="color: rgb(0, 0, 0); font-family: "times new roman", times, serif; font-size: 20px;">- Dedicated 18-bit x 18-bit multiplier blocks</span></p><p style="margin-right: 0px" dir="ltr"><span style="color: rgb(0, 0, 0); font-family: "times new roman", times, serif; font-size: 20px;">- Fast look-ahead carry logic chains</span></p></blockquote><p style="margin-right: 0px" dir="ltr"></p><div><font color="#000000" face="times new roman, times, serif"><span style="font-size: 20px;"><br></span></font></div><ul><li><span style="color: rgb(0, 0, 0); font-family: "times new roman", times, serif; font-size: 20px;">Flexible Logic Resources</span></li></ul><p></p><blockquote style="margin: 0 0 0 40px; border: none; padding: 0px;"><p style="margin-right: 0px" dir="ltr"><span style="color: rgb(0, 0, 0); font-family: "times new roman", times, serif; font-size: 20px;">- Up to 93,184 internal registers / latches with Clock Enable</span></p><p style="margin-right: 0px" dir="ltr"><span style="color: rgb(0, 0, 0); font-family: "times new roman", times, serif; font-size: 20px;">- Up to 93,184 look-up tables (LUTs) or cascadable 16-bit shift registers</span></p><p style="margin-right: 0px" dir="ltr"><span style="color: rgb(0, 0, 0); font-family: "times new roman", times, serif; font-size: 20px;">- Wide multiplexers and wide-input function support</span></p><p style="margin-right: 0px" dir="ltr"><span style="color: rgb(0, 0, 0); font-family: "times new roman", times, serif; font-size: 20px;">- Horizontal cascade chain and sum-of-products support</span></p><p style="margin-right: 0px" dir="ltr"><span style="color: rgb(0, 0, 0); font-family: "times new roman", times, serif; font-size: 20px;">- Internal 3-state bussing</span></p></blockquote><p style="margin-right: 0px" dir="ltr"></p><div><font color="#000000" face="times new roman, times, serif"><span style="font-size: 20px;"><br></span></font></div><ul><li><span style="color: rgb(0, 0, 0); font-family: "times new roman", times, serif; font-size: 20px;">High-Performance Clock Management Circuitry</span></li></ul><p></p><blockquote style="margin: 0 0 0 40px; border: none; padding: 0px;"><p style="margin-right: 0px" dir="ltr"><span style="color: rgb(0, 0, 0); font-family: "times new roman", times, serif; font-size: 20px;">- Up to 12 DCM (Digital Clock Manager) modules</span></p><p style="margin-right: 0px" dir="ltr"><span style="color: rgb(0, 0, 0); font-family: "times new roman", times, serif; font-size: 20px;">· Precise clock de-skew</span></p><p style="margin-right: 0px" dir="ltr"><span style="color: rgb(0, 0, 0); font-family: "times new roman", times, serif; font-size: 20px;">· Flexible frequency synthesis</span></p><p style="margin-right: 0px" dir="ltr"><span style="color: rgb(0, 0, 0); font-family: "times new roman", times, serif; font-size: 20px;">· High-resolution phase shifting</span></p><p style="margin-right: 0px" dir="ltr"><span style="color: rgb(0, 0, 0); font-family: "times new roman", times, serif; font-size: 20px;">- 16 global clock multiplexer buffers</span></p></blockquote><p style="margin-right: 0px" dir="ltr"></p><div><font color="#000000" face="times new roman, times, serif"><span style="font-size: 20px;"><br></span></font></div><ul><li><span style="color: rgb(0, 0, 0); font-family: "times new roman", times, serif; font-size: 20px;">Active Interconnect Technology</span></li></ul><p></p><blockquote style="margin: 0 0 0 40px; border: none; padding: 0px;"><p style="margin-right: 0px" dir="ltr"><span style="color: rgb(0, 0, 0); font-family: "times new roman", times, serif; font-size: 20px;">- Fourth generation segmented routing structure</span></p><p style="margin-right: 0px" dir="ltr"><span style="color: rgb(0, 0, 0); font-family: "times new roman", times, serif; font-size: 20px;">- Predictable, fast routing delay, independent of fanout</span></p></blockquote><p style="margin-right: 0px" dir="ltr"></p><div><font color="#000000" face="times new roman, times, serif"><span style="font-size: 20px;"><br></span></font></div><ul><li><span style="color: rgb(0, 0, 0); font-family: "times new roman", times, serif; font-size: 20px;">SelectIO™-Ultra Technology</span></li></ul><p></p><blockquote style="margin: 0 0 0 40px; border: none; padding: 0px;"><p style="margin-right: 0px" dir="ltr"><span style="color: rgb(0, 0, 0); font-family: "times new roman", times, serif; font-size: 20px;">- Up to 1,108 user I/Os</span></p><p style="margin-right: 0px" dir="ltr"><span style="color: rgb(0, 0, 0); font-family: "times new roman", times, serif; font-size: 20px;">- 19 single-ended and six differential standards</span></p><p style="margin-right: 0px" dir="ltr"><span style="color: rgb(0, 0, 0); font-family: "times new roman", times, serif; font-size: 20px;">- Programmable sink current (2 mA to 24 mA) per I/O</span></p><p style="margin-right: 0px" dir="ltr"><span style="color: rgb(0, 0, 0); font-family: "times new roman", times, serif; font-size: 20px;">- Digitally Controlled Impedance (DCI) I/O: on-chip termination resistors for single-ended I/O standards</span></p><p style="margin-right: 0px" dir="ltr"><span style="color: rgb(0, 0, 0); font-family: "times new roman", times, serif; font-size: 20px;">- PCI-X compatible (133 MHz and 66 MHz) at 3.3V</span></p><p style="margin-right: 0px" dir="ltr"><span style="color: rgb(0, 0, 0); font-family: "times new roman", times, serif; font-size: 20px;">- PCI compliant (66 MHz and 33 MHz) at 3.3V</span></p><p style="margin-right: 0px" dir="ltr"><span style="color: rgb(0, 0, 0); font-family: "times new roman", times, serif; font-size: 20px;">- CardBus compliant (33 MHz) at 3.3V</span></p><p style="margin-right: 0px" dir="ltr"><span style="color: rgb(0, 0, 0); font-family: "times new roman", times, serif; font-size: 20px;">- Differential Signaling</span></p><p style="margin-right: 0px" dir="ltr"><span style="color: rgb(0, 0, 0); font-family: "times new roman", times, serif; font-size: 20px;">· 840 Mb/s Low-Voltage Differential Signaling I/O (LVDS) with current mode drivers</span></p><p style="margin-right: 0px" dir="ltr"><span style="color: rgb(0, 0, 0); font-family: "times new roman", times, serif; font-size: 20px;">· Bus LVDS I/O</span></p><p style="margin-right: 0px" dir="ltr"><span style="color: rgb(0, 0, 0); font-family: "times new roman", times, serif; font-size: 20px;">· Lightning Data Transport (LDT) I/O with current driver buffers</span></p><p style="margin-right: 0px" dir="ltr"><span style="color: rgb(0, 0, 0); font-family: "times new roman", times, serif; font-size: 20px;">· Low-Voltage Positive Emitter-Coupled Logic (LVPECL) I/O</span></p><p style="margin-right: 0px" dir="ltr"><span style="color: rgb(0, 0, 0); font-family: "times new roman", times, serif; font-size: 20px;">· Built-in DDR input and output registers</span></p><p style="margin-right: 0px" dir="ltr"><span style="color: rgb(0, 0, 0); font-family: "times new roman", times, serif; font-size: 20px;">- Proprietary high-performance SelectLink Technology</span></p><p style="margin-right: 0px" dir="ltr"><span style="color: rgb(0, 0, 0); font-family: "times new roman", times, serif; font-size: 20px;">· High-bandwidth data path</span></p><p style="margin-right: 0px" dir="ltr"><span style="color: rgb(0, 0, 0); font-family: "times new roman", times, serif; font-size: 20px;">· Double Data Rate (DDR) link</span></p><p style="margin-right: 0px" dir="ltr"><span style="color: rgb(0, 0, 0); font-family: "times new roman", times, serif; font-size: 20px;">· Web-based HDL generation methodology</span></p></blockquote><p style="margin-right: 0px" dir="ltr"></p><div><font color="#000000" face="times new roman, times, serif"><span style="font-size: 20px;"><br></span></font></div><ul><li><span style="color: rgb(0, 0, 0); font-family: "times new roman", times, serif; font-size: 20px;">Supported by Xilinx Foundation™ and Alliance Series™ Development Systems</span></li></ul><p></p><blockquote style="margin: 0 0 0 40px; border: none; padding: 0px;"><p style="margin-right: 0px" dir="ltr"><span style="color: rgb(0, 0, 0); font-family: "times new roman", times, serif; font-size: 20px;">- Integrated VHDL and Verilog design flows</span></p><p style="margin-right: 0px" dir="ltr"><span style="color: rgb(0, 0, 0); font-family: "times new roman", times, serif; font-size: 20px;">- Compilation of 10M system gates designs</span></p><p style="margin-right: 0px" dir="ltr"><span style="color: rgb(0, 0, 0); font-family: "times new roman", times, serif; font-size: 20px;">- Internet Team Design (ITD) tool</span></p></blockquote><p style="margin-right: 0px" dir="ltr"></p><div><font color="#000000" face="times new roman, times, serif"><span style="font-size: 20px;"><br></span></font></div><ul><li><span style="color: rgb(0, 0, 0); font-family: "times new roman", times, serif; font-size: 20px;">SRAM-Based In-System Configuration</span></li></ul><p></p><blockquote style="margin: 0 0 0 40px; border: none; padding: 0px;"><p style="margin-right: 0px" dir="ltr"><span style="color: rgb(0, 0, 0); font-family: "times new roman", times, serif; font-size: 20px;">- Fast SelectMAP configuration</span></p><p style="margin-right: 0px" dir="ltr"><span style="color: rgb(0, 0, 0); font-family: "times new roman", times, serif; font-size: 20px;">- Triple Data Encryption Standard (DES) security option (Bitstream Encryption)</span></p><p style="margin-right: 0px" dir="ltr"><span style="color: rgb(0, 0, 0); font-family: "times new roman", times, serif; font-size: 20px;">- IEEE 1532 support</span></p><p style="margin-right: 0px" dir="ltr"><span style="color: rgb(0, 0, 0); font-family: "times new roman", times, serif; font-size: 20px;">- Partial reconfiguration</span></p><p style="margin-right: 0px" dir="ltr"><span style="color: rgb(0, 0, 0); font-family: "times new roman", times, serif; font-size: 20px;">- Unlimited reprogrammability</span></p><p style="margin-right: 0px" dir="ltr"><span style="color: rgb(0, 0, 0); font-family: "times new roman", times, serif; font-size: 20px;">- Readback capability</span></p></blockquote><p style="margin-right: 0px" dir="ltr"></p><div><font color="#000000" face="times new roman, times, serif"><span style="font-size: 20px;"><br></span></font></div><ul><li><span style="color: rgb(0, 0, 0); font-family: "times new roman", times, serif; font-size: 20px;">0.15 µm 8-Layer Metal Process with 0.12 µm High-Speed Transistors</span></li></ul><div><font color="#000000" face="times new roman, times, serif"><span style="font-size: 20px;"><br></span></font></div><ul><li><span style="color: rgb(0, 0, 0); font-family: "times new roman", times, serif; font-size: 20px;">1.5V (VCCINT) Core Power Supply, Dedicated 3.3V VCCAUX Auxiliary and VCCO I/O Power Supplies</span></li></ul><div><font color="#000000" face="times new roman, times, serif"><span style="font-size: 20px;"><br></span></font></div><ul><li><span style="color: rgb(0, 0, 0); font-family: "times new roman", times, serif; font-size: 20px;">IEEE 1149.1 Compatible Boundary-Scan Logic Support</span></li></ul><div><font color="#000000" face="times new roman, times, serif"><span style="font-size: 20px;"><br></span></font></div><ul><li><span style="color: rgb(0, 0, 0); font-family: "times new roman", times, serif; font-size: 20px;">Flip-Chip and Wire-Bond Ball Grid Array (BGA) Packages in Three Standard Fine Pitches (0.80 mm, 1.00 mm, and 1.27 mm)</span></li></ul><br><font color="#000000" face="times new roman, times, serif"><span style="font-size: 20px"><br><br></span></font><br><p></p>
<div align="center"><strong><span style="font-family: "times new roman", serif"><span style="font-size: 16pt">Sold as is with 30 day Right of Return, only pictured items included</span></span></strong><br><strong><span style="font-family: "times new roman", serif"><span style="font-size: 16pt">Easy return/refund for any reason</span></span></strong><br><span style="color: rgb(39,87,141)"><span style="font-family: "times new roman", serif"><span style="font-size: 18pt">Anacapa Equipment</span></span></span><span style="font-family: "times new roman", serif"></span></div>
<div style="text-align: left"><strong><span style="font-family: "times new roman", serif"><span style="font-size: 12pt">RETURNS</span></span></strong><span style="font-family: "times new roman", serif"><span style="font-size: 12pt"> <br>Anacapa Equipment Brokers, Inc. (“Seller”) strives to offer excellent customer service. You may return any equipment purchased from us for any reason within thirty (30) days after your receipt of the equipment for a full refund of the purchase price, provided that returned items are received in the same condition as sent. We DO NOT ship internationally. If you are using a freight forwarder then returns are VOID. </span></span><br><strong><span style="font-family: "times new roman", serif"><span style="font-size: 12pt">SHIPPING </span></span></strong><span style="font-family: "times new roman", serif"><span style="font-size: 12pt"> All equipment purchased is shipped within one (1) business day (subject to freight availability) after receipt of payment and is shipped FOB place of shipment. We only charge actual shipping cost. If eBay overcharges for shipping, we issue an immediate refund for the difference. If you are undercharged, we will absorb the cost. <span style="background: white">We DO NOT ship internationally. IF you are using a freight forwarder then returns are VOID. </span></span></span><br><strong><span style="font-family: "times new roman", serif"><span style="font-size: 12pt">LIMITED WARRANTY</span></span></strong><span style="font-family: "times new roman", serif"><span style="font-size: 12pt"> <br>Buyer acknowledges that the equipment is being sold “as is" and without any warranty of merchantability or fitness for a particular use. The entire risk as to the quality and performance of the equipment is with the Buyer. Should the equipment prove defective following its purchase the Buyer and not the Seller, manufacturer, distributor, or retailer assumes the entire cost of all necessary servicing or repair. Buyer may inspect the equipment prior to purchase and placement of the order. Failure to inspect prior to placement of an order is deemed a waiver of Buyer’s right to inspect. Buyer is responsible for determining the suitability of the equipment for its application. Seller assumes no liability for the use or misuse of any equipment purchased by Buyer. It is assumed that the equipment will be installed and operated by qualified personnel. The Buyer agrees that the Seller shall not be held responsible or liable for any injuries or damages, whether incidental or consequential, associated in any way with the equipment purchased. <strong><em><u>The Buyer, by purchasing this equipment, indicates its acknowledgment of, and agreement, to the terms of this limited warranty</u></em></strong>.</span></span><br><strong><span style="font-family: "times new roman", serif"><span style="font-size: 12pt">INDEMNITY</span></span></strong><span style="font-family: "times new roman", serif"><span style="font-size: 12pt"> </span></span><br><span style="font-family: "times new roman", serif"><span style="font-size: 12pt">Buyer shall be solely liable for, and shall defend, indemnify, and hold Seller, its Affiliates, and all of their respective directors, officers, employees, agents, and independent contractors (“Indemnitees”) harmless from and against any and all damages, liabilities, injuries, losses, costs (including reasonable attorneys and experts fees at trial and on appeal), and expenses which may be incurred by, asserted against, or recoverable from any Indemnitee as a result of any actual or threatened action, suit or proceeding arising out of or relating in any way to the purchase of equipment from Seller. The validity and interpretation of this Agreement and the enforcement thereof shall be governed by the laws of the State of California without regard to any principles governing conflicts of laws. Any dispute arising from the purchase of equipment from Seller must be resolved in the State Courts of California.</span></span> <span style="font-family: "times new roman", serif"></span></div>
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